Essay regarding Solved Queries on Batching and EOQ

Homework: Batching and EOQ

Operations Management

Instructor: Cuihong Li

Name: Gupta, Randeep

Instruction:

1) Print a message above.

2) Please turn in your work at the beginning of the class on the due date. 3) You need to present not only the response to each problem but also how the response is reached, for example , the formula, calculation, and explanation when necessary. 4) Total items: 13

1 ) JCL Inc. is a key chip production firm that sells usana products to computer manufacturers like Dell, HP, and others. In simplified terms, chip making at JCL Inc. consists of three simple operations: adding, patterning, and etching. Adding: Using substance vapor deposition (CVD) technology, an protecting material is deposited around the wafer surface, forming a thin layer of stable material within the chip. Patterning: Photolithography assignments a microscopic circuit pattern on the wafer surface, which has a light-sensitive chemical like the emulsion on photographic film. It is repeated frequently as each layer in the chip is made. Etching: Etching removes selected material in the chip surface to create these devices structures. The next table lists the required control times and setup instances at each from the steps. There exists unlimited space for stream inventory among these steps. Assume that the unit of production is actually a wafer, from where individual chips are cut at a later stage. Note: A Setup can simply begin after the batch is here at the machine. Process Step

1 Depositing

2 Patterning

3 Decoration

Setup time

0 min.

30 min.

0 min.

Processing time

0. 45 min. /unit

0. twenty-five min. /unit

0. 30 min. /unit

a. What is the logjam step and process ability (in models per hour) with a group size of 90 wafers? (2') �

Adding

Patterning

Decoration

Capacity

1/0. 45 = 2 . 2222

100/(100*0. 25 & 30) = 1 . 8182

1/0. 30 = 3. 3333

Ability (Units/Hr)

133. 33

109. 09

two hundred

Bottleneck stage = Patterning.

b. What is the bottleneck step and process capability (in...